The present invention relates to a Linear Dropout (LDO) regulator, and more specifically, to an LDO regulator with an improved transient response.
Recent years have seen tremendous advancements in the field of electronic circuits. One such advancement is in the area of providing a supply voltage used to operate electronic circuits. The supply voltage may vary due to various factors such as changes in the load of the circuit to which the voltage is being supplied, temperature variations, aging, and so forth. Variation of the supply voltage can affect the operation of the electronic circuit. Thus, a voltage regulator is used to maintain the output of the supply voltage at a predetermined value. Over the years, a few different types of regulators have been developed, such as a standard regulator, a low drop-out (LDO) regulator, and a quasi-LDO regulator, with LDO regulators being the most widely used.
FIG. 1 is schematic circuit diagram of a conventional LDO regulator 100. The LDO regulator 100 includes an error amplifier 102, a pass-transistor 104, a capacitor C1, and resistance network R1, R2.
The error amplifier 102 is connected to the gate of the pass-transistor 104. The source of the pass-transistor 104 is connected to a voltage supply (VDD) and the drain of the pass-transistor 104 comprises the output terminal of the LDO regulator 100. The capacitor C1, which may be either an internal capacitor or external to the regulator circuit, is connected to the output of LDO regulator 100. The resistance network R1 and R2 also is connected to the output of the LDO regulator 100 and in parallel with the capacitor C1. A node between the resistors R1 and R2 is connected to an input terminal of the error amplifier 102 and provides a scaled-down version of the output voltage to the error amplifier 102. The error amplifier 102 also receives a reference voltage signal that is generated by an external voltage reference circuit. The error amplifier 102 compares the reference voltage signal and the scaled down version of the output voltage signal to generate an error amplified signal, which is provided to the gate terminal of the pass-transistor 104. The error amplified signal is used to maintain the output of the LDO regulator 100 at a predetermined voltage.
The LDO regulator 100 generates a constant output voltage to the load (not shown) by providing the required load current. If the magnitude of the load current increases due to variations in the load, there is a corresponding drop in the magnitude of the output voltage. The drop in the output voltage leads to an increase in the magnitude of the error amplified signal generated by the error amplifier 102. The increase in the error amplified signal in turn increases the magnitude of the source-gate voltage of the pass-transistor 104, causing a corresponding increase in the magnitude of the drain current of the pass-transistor 104, and the increase in the drain current pulls up the output voltage. Thus, the magnitude of the output voltage signal is maintained at the predetermined voltage. The capacitor connected to the output terminal improves the transient response of the LDO regulator 100.
During steady-state operation, the magnitude of the output voltage signal is maintained at the predetermined value and the output capacitor C1 is charged to the magnitude of the output voltage signal. If the current of the load circuit changes abruptly and the main regulation loop, formed by the error amplifier 102, pass-transistor 104 and resistor network R1 and R2, may not respond quickly because it has a bandwidth limitation, the capacitor C1 provides the extra charge required by the load. As a result, the magnitude of the output voltage decreases or increases from the predetermined voltage value.
The magnitude of output voltage drop or rise can be improved by either increasing the bandwidth/speed of the main regulation loop or by increasing the value of the capacitor C1. However, such changes have associated constraints such as power consumption, silicon area, and overall cost of the system. To increase the bandwidth or speed of the main regulation loop, the DC current should be increased, which results in higher power consumption of the system and also increased die area. The capacitor C1 can be realized as either an internal or external capacitor. An external capacitor increases cost, while an internal capacitor cannot be made very large because that would require significant additional die area. Thus, there is a need for a circuit that improves the transient response of the LDO regulator yet avoids the above-mentioned constraints.